[Interview] Update on future technologies for advanced computation and functionality

In 2024, you coordinated a report on future technologies for advanced computation and functionality. Why was it important to provide an update one year later?

Because the technology landscape moved significantly within a year. AI workloads, heterogeneous integration, packaging, photonics, power electronics, and quantum technologies all evolved very fast, and new roadmaps emerged. At the same time, Europe’s strategic gaps and opportunities shifted. Updating the report in 2025 ensured that our recommendations remained relevant, evidence‑based, and aligned with the most recent technological and geopolitical developments.

On future technologies for advanced computation, what new trends did you identify?

We saw a clear shift: AI is now driving the entire roadmap. The main bottlenecks have moved from compute to memory bandwidth, data movement, and thermal constraints, so future architectures are becoming much more memory‑centric. We also observed a strong acceleration in heterogeneous integration and chiplet‑based design, especially with hybrid bonding becoming mainstream. At the device level, new concepts like CFETs and backside power delivery are emerging to support higher‑density logic. And finally, fabrics such as optical interconnects and CXL‑based links are gaining importance as data movement becomes the dominant limiter. Overall, the trend is toward full system‑level co‑optimization rather than isolated device scaling.

With the AI-driven compute explosion, what are the main limitations we should anticipate?

With AI driving compute to unprecedented heights, the main limitations won’t come from the processors themselves but from the system around them. The biggest bottleneck is memory bandwidth and data movement. Moving data now costs more energy than computing it. We also face thermal and power constraints, because dense 3D architectures generate heat that is increasingly difficult to remove. A third limitation is the interconnect fabric: electrical links can’t scale fast enough and are not so energy efficient, so we need new solutions like co‑packaged optics. In short, AI isn’t limited by transistors anymore. It’s limited by bandwidth, energy, and heat.

About advanced functionality, what are the main challenges ahead?

For advanced functionality, the biggest challenges are on the integration and system side. We see increasing complexity in heterogeneous integration, where very different materials and device types (sensors, photonics, power, energy‑harvesting, RF) must sometime be co‑packaged reliably. This introduces issues with material compatibility, yield, and long‑term reliability.

A second challenge is that many of these fields suffer from high market fragmentation. Applications range from healthcare to automotive to industrial IoT, each with very different specifications, volumes, and cost points. This fragmentation makes it hard to develop unified platforms, slows down standardization, and reduces the economic incentive for large‑scale manufacturing.

We also see limitations in packaging and pilot‑line capacity, especially for MEMS, photonics, and mixed‑signal modules where Europe still lacks volume manufacturing capability. And finally, achieving ultra‑low‑power operation, for edge AI, sensing, and IoT, will require advances in energy harvesting, storage, and system‑level power management, which are still not mature.

For future technologies, how to combine high-performance computation and diversified functionalities?

To combine high‑performance computation with diversified functionalities, the key is advanced 3D and heterogeneous integration. Instead of relying on large monolithic chips, we now disaggregate logic, memory, photonics, sensors, RF, and power devices into optimized chiplets and then re‑assemble them using 2.5D/3D stacking, hybrid bonding, and high‑density interconnects. This allows each technology to use the most suitable process while still achieving the bandwidth, latency, and energy efficiency required for the specific application.

At the same time, combining these domains requires system‑level co‑design. Compute, memory, interconnects, power delivery, thermal solutions, and functional modules must be optimized together rather than in isolation. In the deliverable, this is why advanced packaging is described not as a back‑end step but as a strategic enabler that bridges high‑performance computation with sensing, photonics, energy harvesting, and power electronics. Ultimately, the future lies in modular, chiplet‑based architectures where computation and functionality can be mixed and matched depending on the application.

You also mapped the strength and weakness of European and non-European countries. What are the opportunities for Europe in these key areas?

There are several clear opportunities for Europe when you look at the strengths and gaps of global ecosystems. Europe has an excellent research base in advanced CMOS, photonics, MEMS, wide‑bandgap power electronics, and heterogeneous integration, but it lacks large‑scale manufacturing, advanced packaging capacity, and high‑volume system integration. This creates two major opportunities.

First, Europe can leverage international partnerships to accelerate access to industrial‑scale capabilities. For example, collaborating with the US on EDA, chiplet standards, and quantum; with Japan on materials, MRAM, and SiC/GaN; with Korea on memory and HBM; and with Taiwan for advanced packaging and 3D integration. These partners complement Europe’s research strengths and help close structural gaps in manufacturing and packaging.

Second, Europe can turn its own research strengths into industrial leadership by focusing on a few high‑impact domains where it is already competitive: advanced packaging and heterogeneous integration, photonics and co‑packaged optics, wide‑bandgap and ultra‑wide‑bandgap power electronics, memory‑centric compute, and quantum‑classical hybrid systems. These areas are strategically important, aligned with global demand, and benefit from Europe’s technological excellence.

If Europe aligns investment behind these domains and pairs it with targeted international cooperation, it can strengthen its resilience and gain leadership in the next wave of semiconductor technologies.

You also provide recommendations in your deliverable. Can you tell us more? 

In the deliverable, we make a set of focused recommendations aimed at strengthening Europe’s position in both advanced computation and advanced functionality. The key message is that Europe needs to double down on advanced packaging and heterogeneous integration, because this is now the strategic enabler linking devices, memory, photonics, sensors, and power electronics into full systems. Strengthening pilot lines and building industrial‑scale 2.5D/3D integration capability is essential for Europe to translate its strong research base into products.

We also recommend investing in memory‑centric compute (HBM, near‑memory and in‑memory architectures) since AI scaling is now limited by bandwidth and data movement. Europe is strong in research here but needs partnerships, especially with Korea, the US, and Japan, to access high‑volume memory ecosystems.

Another important recommendation is to expand Europe’s leadership in photonics, particularly co‑packaged optics and integrated photonics for datacenter interconnects. This is a high‑growth area where Europe has strong R&D but lacks manufacturing depth.

Finally, we emphasize the need to strengthen skills, design tools, and AI‑enabled EDA. As systems become more heterogeneous, engineers need competencies in multiphysics co‑design, chiplet partitioning, packaging‑aware architecture, and AI‑driven design automation. Skills development is therefore not optional. It’s a core enabler of Europe’s semiconductor strategy.

Overall, the recommendations call for pairing strong European research with targeted international cooperation, and for building the packaging, memory, photonics, and system‑integration infrastructure needed to move from technology leadership to industrial leadership.